Behavioral Modeling of CMOS Digital Potentiometers Using VHDL-AMS

This paper focuses on analysis and behavioral modeling of CMOS RDAC (redundant disk array controller) potentio-meters, using string DAC (digital-to-analog converter) or Kelvin divider architecture. The model is developed by using VHDLAMS language and accurately reflects the basic DC and AC transfer characteristic at various modes of operation for linear and nonlinear increment/decrement of the wiper. The created model is coded by using a style, combining structural and behavioral elements. The structural description is the net-list of the model and the behavioral description consists of simultaneous statements and some event-driven techniques to represent the behavior of the real devices. For verification check the model parameters are extracted for the single-stage AD5235 and triple-stage AD5143 RDACs from Analog Devices as examples. The workability of the proposed models is verified by simulation and experimental testing of sample electronic circuits. The comparative analysis shows that the achieved relative error, between the simulation and the experimental results at nominal resistance of 250k Omega is not larger than 3%. Moreover, an error of 3% is quite acceptable, considering the technological tolerances of the parameters.