A data scheduler for multi-context reconfigurable architectures

In this paper, we present an approach to the problem of data scheduling for multi-context reconfigurable architectures targeting DSP applications. The main goal is to improve applications execution time, through the integration of the data scheduler within a compilation framework specifically conceived for these architectures. Some amount of on-chip data storage is assumed to be available in the reconfigurable architecture. Therefore the data scheduler tries to optimally exploit this storage, saving data transfers between on-chip and external memories. In order to do this, specific algorithms for data placement and replacement have been designed. We also show that a suitable data scheduling could decrease the number of operations required to implement the dynamic reconfiguration of the system.