Reducing cache conflicts by multi-level cache partitioning and array elements mapping

被引:1
|
作者
Chang, CY
Sheu, JP
Chen, HC
机构
[1] Aletheia Univ, Dept Comp & Informat Sci, Taipei, Taiwan
[2] Natl Cent Univ, Dept Comp Sci & Informat Engn, Chungli 32054, Taiwan
来源
JOURNAL OF SUPERCOMPUTING | 2002年 / 22卷 / 02期
关键词
cache conflict; array padding; cache partitioning; multi-level cache; direct mapping; loop tiling;
D O I
10.1023/A:1014982819342
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This article presents an algorithm to reduce cache conflicts and improve cache localities. The proposed algorithm analyzes locality reference space for each reference pattern, partitions the multi-level cache into several parts with different sizes, and then maps array data onto the scheduled cache positions to eliminate cache conflicts. A greedy method for rearranging array variables in declared statement is also developed, to reduce the memory overhead for mapping arrays onto a partitioned cache. Besides, loop tiling and the proposed schemes are combined to exploit opportunities for both temporal and spatial reuse. Atom is used as a tool to develop a simulation of the behavior of the direct-mapping cache to demonstrate that our approach is effective at reducing number of cache conflicts and exploiting cache localities. Experimental results reveal that applying the cache partitioning scheme can greatly reduce the cache conflicts and thus save program execution time in both single-level cache and multi-level cache hierarchies.
引用
收藏
页码:197 / 219
页数:23
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