Vector processing in scalar processors for signal processing algorithms

被引：0
|
作者：
Brady, MT [1 ]
Trelewicz, JQ [1 ]
Mitchell, JL [1 ]
机构：
[1] IBM Printing Syst Div, Boulder, CO 80301 USA
来源：
2001 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I-VI, PROCEEDINGS: VOL I: SPEECH PROCESSING 1; VOL II: SPEECH PROCESSING 2 IND TECHNOL TRACK DESIGN & IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS NEURALNETWORKS FOR SIGNAL PROCESSING; VOL III: IMAGE & MULTIDIMENSIONAL SIGNAL PROCESSING MULTIMEDIA SIGNAL PROCESSING - VOL IV: SIGNAL PROCESSING FOR COMMUNICATIONS; VOL V: SIGNAL PROCESSING EDUCATION SENSOR ARRAY & MULTICHANNEL SIGNAL PROCESSING AUDIO & ELECTROACOUSTICS; VOL VI: SIGNAL PROCESSING THEORY & METHODS STUDENT FORUM | 2001年
关键词：
D O I：
暂无
中图分类号：
O42 [声学];
学科分类号：
070206 ; 082403 ;
摘要：
Product requirements often dictate the use of off-the-shelf processors for very fast signal processing applications. Additionally, restrictions on cost, power, or size/weight may preclude the use of specialized vector processors for implementation of the algorithms. We discuss a new method for performing signed parallel processing in scalar, off-the-shelf processors for integerized signal processing algorithms. Uniform data precision may be used, but is not required for the method. It is shown that the reduction in execution cycles resulting from this implementation is approximately linear in the size of the registers, divided by the precision required.
引用
收藏
页码：933 / 936
页数：4
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