CMOS X-Ray Detector With Column-Parallel 14.3-bit Extended-Counting ADCs

This paper presents a CMOS X-ray detector with 14.3-bit column-parallel extended-counting analog-to-digital converters (EC-ADCs). The CMOS X-ray detector employs column-parallel EC-ADCs with a built-in analog binning function for high gray-scale resolution and small silicon area. The total area of the 14.3-bit EC-ADC and digital logic circuits is only 100 mu m x 1100 mu m. The Delta Sigma modulator in the EC-ADC simultaneously performs the upper 3-bit conversion and the analog binning operation. To reduce the fixed-pattern noise (FPN) from the ADC and the pixel, we adopt the digital correlated-double sampling technique. A bias circuit for the column-parallel readout architecture in a large-area CMOS X-ray detector is proposed to improve the uniformity among column ADCs. Simulation results show that the uniformity of output voltages among column ADCs is improved to 50 times the uniformity in the conventional bias circuit. The proposed CMOS X-ray detector has been fabricated using a 0.35-mu m CMOS process. The measured differential column FPN and random noise without X-ray exposure at the frame rate of 60 frames/s are 3.10 and 5.17 least significant bit, respectively. The measured dynamic range is 68.3 dB under the same conditions.