A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS

被引：0

作者：

Furuta, Masanori ^{[1
]}

Okuni, Hidenori ^{[1
]}

Hosoya, Masahiro ^{[1
]}

Sai, Akihide ^{[1
]}

Matsuno, Junya ^{[1
]}

Saigusa, Shigehito ^{[1
]}

Itakura, Tetsuro ^{[1
]}

机构：

[1] Toshiba Co Ltd, Corp Res & Dev Ctr, Kawasaki, Kanagawa 2128582, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2015年 / E98A卷 / 02期

关键词：

time-interleaved; SAR; ADC; dynamic; T/H circuit; high-speed; low-power; AMPLIFIER; ADC;

D O I：

10.1587/transfun.E98.A.492

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an analog front-end circuit for a 60-GHz proximity wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65 nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224 mW Power consumption.

引用

页码：492 / 499

页数：8

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