Development of a new leadframe-type chip scale package

被引:0
|
作者
Chiang, CL
Huang, HC
Lee, RS
Cheng, PH
机构
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The explosive growth of high density and low cost electronic products have a tremendous impact on the electronic packaging industry. Recently, chip scale packaging(CSP) technology is proposed for higher density of IC packaging. A new low cost leadframe-type CSP has been developed and proved itself suitable for mass production. Instead of conventional transfer molding, a liquid epoxy dispension process is applied on a pre-dammed LOC-leadframe on which the bare chip was mounted and wire bonded in a LOC process. A seperated process is then used to finish the CSP package. Considering the CTE mismatch issue, this CSP package is more reliable than those with conventional transfer molding encapsulation. Due to short trace and exposure of IC chip, This CSP provides a better electrical and thermal performances. Besides, a pre-defined metal ring will also help to standardize the CSP's dimension.
引用
收藏
页码:397 / 400
页数:4
相关论文
共 50 条
  • [1] Assembly process development of stacked multi-chip leadframe package
    Yao, YF
    Njoman, B
    Chua, KH
    [J]. 6TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, PROCEEDINGS (EPTC 2004), 2004, : 25 - 29
  • [2] Development of a Low CTE Chip Scale Package
    Yamada, Tomoyuki
    Fukui, Masahiro
    Terada, Kenji
    Harazono, Masaaki
    Reynolds, Charles
    Audet, Jean
    Iruvanti, Sushumna
    Liu, Hsichang
    Moore, Scott
    Pan, Yi
    Zhang, Hongqing
    [J]. 2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 944 - 948
  • [3] New stacked chip-scale package
    不详
    [J]. SOLID STATE TECHNOLOGY, 2001, 44 (03) : 42 - 42
  • [4] Development of subtractive wafer level chip scale package
    不详
    [J]. NEC RESEARCH & DEVELOPMENT, 2001, 42 (02): : 251 - 251
  • [5] Chip-Package-Board Reliability of System-in-Package Using Laminate Chip Embedding Technology Based on Cu Leadframe
    Fruehauf, Peter
    Munding, Andreas
    Pressel, Klaus
    Schwarz, Patrick
    Vogt, Michael
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2020, 10 (01): : 44 - 56
  • [6] New chip scale package for medical applications: ''Plip-chip''
    Val, CM
    [J]. 1996 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, 1996, 2920 : 236 - 242
  • [7] Chip-package-board reliability of System-in-Package using laminate chip embedding technology based on Cu leadframe
    Fruehauf, Peter
    Munding, Andreas
    Pressel, Klaus
    Vogt, Michael
    Schwarz, Patrick
    [J]. 2018 7TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), 2018,
  • [8] New chip scale package with CTE matching to the board
    Schueller, RD
    Geissinger, J
    [J]. PROCEEDINGS OF THE 1997 1ST ELECTRONIC PACKAGING TECHNOLOGY CONFERENCE, 1997, : 219 - 227
  • [9] New chip scale package with CTE matching to the board
    Schueller, RD
    [J]. TWENTY FIRST IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM, 1997, : 205 - 215
  • [10] A New Current Crowding Phenomenon for Flip-Chip-on-Leadframe (FCOL) Package and its Impact on Electromigration Reliability
    Ankamah-Kusi, Sylvester
    Sreenivasan, Koduri
    Murugan, Rajen
    [J]. 2022 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS (EDAPS), 2022,