Low VT metal-gate/high-k nMOSFETs -: PBTI dependence and VT tune-ability on La/Dy-capping layer locations and laser annealing conditions

被引：0

作者：

Chang, S. Z. ^{[1
]}

Hoffmann, T. Y.

Yu, H. Y. ^{[2
]}

Aoulaiche, M. ^{[3
]}

Rohr, E.

Adelmann, C.

Kaczer, B.

Delabie, A.

Favia, P.

Van Elshoct, S.

Kubicek, S.

Scharm, T.

Witters, T.

Ragnarsson, L. -A.

Wang, X. P.

Cho, H. -J. ^{[4
]}

Mueller, M. ^{[5
]}

Chiarella, T.

Absil, P.

Biesemans, S.

机构：

[1] Nanyang Technol Univ, TSMC, Singapore, Singapore

[2] Nanyang Technol Univ, EEE, Singapore, Singapore

[3] EE Katholieke Univ Leuven, B-3000 Louvain, Belgium

[4] Samsung, Seoul, South Korea

[5] NXP, TSMC Res Ctr, B-3001 Louvain, Belgium

来源：

2008 SYMPOSIUM ON VLSI TECHNOLOGY | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper provides a comprehensive study of the abnormal PBTI behaviors recently observed in La/Dy-capped high-k films in low-V-T nMOSFETs. We found that process details in thermal budget (or dielectric intermixing) and oxygen content of the metal trigger the onset of these abnormalities. The Delta V-T relaxation during the PBTI recovery period induced by bulk trapping/de-trapping is believed to be oxygen vacancies related, and can be suppressed either by reducing dielectric intermixing with lower laser anneal powers (La above or below HK), or by increasing the oxygen concentration, i.e., TaCNO metal electrode instead of TaCN (La above HK). Putting La below HK can result in a similar V-T time-ability with less thermal budget for intermixing with the IL (with superior PBTI), without loss of current drive-ability. We propose Ta2C/HK/LaO/IL + LLP anneals as an optimum nFETs stack configuration for practical CMOS integration.

引用

页码：49 / +

页数：2