DESIGN OF MULTI-MODE PLL FOR POWER MANAGEMENT IC

被引：0

作者：

Pan, Hong ^{[1
]}

Wu, Xiaobo ^{[1
]}

Song, Shuang ^{[1
]}

Zhao, Menglian ^{[1
]}

Yan, Xiaolang ^{[1
]}

机构：

[1] Zhejiang Univ, Inst VLSI Design, Hangzhou 310027, Peoples R China

来源：

CIICT 2008: PROCEEDINGS OF CHINA-IRELAND INTERNATIONAL CONFERENCE ON INFORMATION AND COMMUNICATIONS TECHNOLOGIES 2008 | 2008年

关键词：

Multi-mode PLL oscillator;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

To improve application flexibility of power management ICs and reduce their peripheral components, a novel Multi-Mode PLL was proposed. This PLL provides 1.7MHz/2.6MHz fixed frequency mode without external clock signal and synchronizing mode with a locked frequency range from 500kHz to 3MHz. In addition, a novel structure of oscillator was introduced to achieve small duty cycle for power management ICs. The chip was designed and fabricated in 1.5 mu m BCD technology. Test results showed that all functions were successfully realized and the main features were consistent with expectations.

引用

页码：615 / 618

页数：4

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