Towards a formal model of hardware synthesized from Verilog

被引：0
|
作者：
Arnold, M [1 ]
Wallace, A [1 ]
Cupal, J [1 ]
Cowles, J [1 ]
Engineer, F [1 ]
机构：
[1] UNIV WYOMING,LARAMIE,WY 82071
来源：
1996 IEEE INTERNATIONAL VERILOG HDL CONFERENCE, PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/IVC.1996.496019
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：60 / 66
页数：7
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