A 0.4ps-rms-jitter 1-3GHz ring-oscillator PLL using phase-noise preamplification

A 1-3GHz tunable multiply-by-8 PLL is implemented in 0.13 mu m CMOS and occupies 0.07mm(2). A proposed fully-differential Gm-C loop filter structure decouples reference spur performance from charge-pump current matching and loop filter leakage, while enables phase error preamplification to lower PLL in-band noise without reducing VCO analog tuning range or increasing loop filter capacitor size. It achieves <-118dBc/Hz PLL in-band noise (>100kHz offset) and 0.4ps-rms jitter (integrated from 3kHz to 300MHz offset) for >= 2.5GHz outputs.