Hardware Acceleration for 3D Image Reconstruction

被引：3
|
作者：
Chaikalis, D. [1 ]
Passalis, G. [1 ]
Sgouros, N. [1 ]
Maroulis, D. [1 ]
Theoharis, T. [1 ]
机构：
[1] Univ Athens, Dept Informat & Telecommun, Panepistimiopolis 15784, Ilisia, Greece
来源：
PCI 2008: 12TH PAN-HELLENIC CONFERENCE ON INFORMATICS, PROCEEDINGS | 2008年
关键词：
D O I：
10.1109/PCI.2008.23
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
This work presents a hardware acceleration scheme for a 3D reconstruction method, targeting demanding dynamic Integrated Imaging applications. The architecture exploits parallel processing and minimizes memory operations by implementing an efficient metric and an extended-access memory scheme. The employed data reutilization technique reduces overall throughput allowing the use of a single FPGA. Results reveal that the hardware system accelerates the software method by an order of magnitude and its processing rate surpasses the typical rate of a dynamic Integral Imaging acquisition system, making it suitable for robust 3D image and video reconstruction applications.
引用
收藏
页码：147 / 151
页数：5
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