Design of Approximate Dividers for Error Tolerant Applications

This paper explores architectural designs of approximate unsigned integer dividers based on restoring and non-restoring algorithms. As the subtractor cell is the basic building of a divider, three designs of approximate subtractors are proposed. These approximate subtractors when used in divider reduce the complexity, power consumption and delay at the cost of lower accuracy. The efficiency of proposed dividers are evaluated by simulating the circuits in 45-nm CMOS technology. The results indicate that the third design of approximate non-restoring and restoring dividers are consuming only 31 % and 33% delay and power respectively as compared to conventional design. The accuracy of proposed designs is analyzed with several error metrics. The approximate restoring dividers are performing superior to non-restoring dividers both in-terms of design parameters and error metrics.