Macro interleaver design for bit interleaved coded modulation with Low-Density Parity-Check codes

Bit interleaved coded modulation (BICM) is a pragmatic approach to achieve power and bandwidth efficient transmission. At this Low-Density Parity-Check codes (LDPCC) can be utilized which are then concatenated with a modulator. The concatenation of LDPCC and modulator is done via a bit interleaver which has the task to spread information. While the matched design of an optimal LDPC degree distribution with respect to a given mapping scheme is well observed it is often assumed that the probabilistic values passed from demodulator to the LDPCC decoder are independent due to the mapping interleaver. However for higher order modulations, e.g. 16-QAM or 256-QAM, more and more bits are getting correlated during the demodulation process. The connectivity of these correlated bits have to be considered during the design of the mapping interleaver with respect to the graph of the concatenated LDPC codes. In this paper, we present the design of mapping interleavers of BICM schemes utilizing LDPC codes. Simulation results show the strong influence of correlated inputs to the performance of LDPC decodes. This correlations can cause a high error floor if the mapping interleaver is not carefully designed.