Thulium Silicate Interfacial Layer for Scalable High-k/Metal Gate Stacks

Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25 +/- 0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density similar to 0.7-2x10(11) cm(-2)eV(-1) was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm(2)/Vs for nFET and 60 cm(2)/Vs for pFET devices, at an inversion charge density of 10(13) cm(-2) and at a total capacitance equivalent thickness of 1.6 nm.