Future chips to achieve extreme performance with new architectures and merged dram and logic

被引：0
|
作者：
Bursky, D
机构：
来源：
ELECTRONIC DESIGN | 1996年 / 44卷 / 18期
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：37 / +
页数：1
相关论文
共 5 条
  • [1] Evaluating DRAM refresh architectures for merged DRAM/logic LSIs
    Ohsawa, T
    Kai, K
    Murakami, K
    IEICE TRANSACTIONS ON ELECTRONICS, 1998, E81C (09) : 1455 - 1462
  • [2] DRAM vendors juggle with new architectures to increase performance
    Child, Jeff
    Electronic Systems Technology and Design/Computer Design's, 1995, 34 (03):
  • [3] Analyzing and reducing the impact of shorter data retention time on the performance of merged DRAM/logic LSIs
    Kai, K
    Inoue, A
    Ohsawa, T
    Murakami, K
    IEICE TRANSACTIONS ON ELECTRONICS, 1998, E81C (09) : 1448 - 1454
  • [4] New ESCAP-type resist with enhanced etch resistance and its application to future DRAM and logic devices
    Conley, W
    Brunsvold, B
    Buehrer, F
    Dellaguardia, R
    Dobuzinsky, D
    Farrell, T
    Ho, H
    Katnani, A
    Keller, R
    Marsh, J
    Muller, P
    Nunes, R
    Ng, H
    Oberschmidt, J
    Pike, M
    Ryan, D
    CotlerWagner, T
    Schulz, R
    Ito, H
    Hofer, D
    Breyta, G
    FenzelAlexander, D
    Wallraff, G
    Opitz, J
    Thackeray, J
    Barclay, G
    Cameron, J
    Lindsay, T
    Cronin, M
    Moynihan, M
    Nour, S
    Georger, J
    Mori, M
    Hagerty, P
    Sinta, R
    Zydowsky, T
    ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XIV, 1997, 3049 : 282 - 299
  • [5] Two-Phase Vapor Chambers with Micropillar Evaporators: A New Approach to Remove Heat from Future High-Performance Chips
    Yuan, Zihao
    Vaartstra, Geoffrey
    Shukla, Prachi
    Said, Mostafa
    Reda, Sherief
    Wang, Evelyn
    Coskun, Ayse K.
    PROCEEDINGS OF THE 2019 EIGHTEENTH IEEE INTERSOCIETY CONFERENCE ON THERMAL AND THERMOMECHANICAL PHENOMENA IN ELECTRONIC SYSTEMS (ITHERM 2019), 2019, : 456 - 464
1