Semi-Analytical Estimation of Intra-Die Variations of Analog Performances of Nano-scale nMOS Transistor

This paper presents a semi analytical technique for estimating the effects of intra-die process variations on the performances of an nMOS transistor. The intra-die process variability sources considered in the work are Random Discrete Dopants (RDD), Channel Length Variation (CLV), Oxide Thickness Variation (OTV) and Mobility Fluctuation (MF). The analog performances which are studied are transconductance g(m), intrinsic speed f(t), thermal noise spectral density S-n and flicker noise spectral density S-f. The estimation technique is based on BSIMIV-SPICE process parameters. The mean and standard deviation of the performance variations are estimated. The estimated results are verified through Monte Carlo (MC)-HSPICE simulation results.