Multi-Cycle CPU Design With FPGA for Teaching of Computer Organization Principle

CPU design with programmable FPGA has become a significant solution for the experiment teaching of computer organization principle. In this paper, the design concept, implementation technique and verification method of a multicycle MIPS CPU are presented. To decrease the CPU design complexity, the hierarchical division approach which divides the CPU into a serial of easy-to-implement modules is proposed. To help the students master the intricate FPGA development process in an easy-to-understand way, the easy-to-hard progressive implementation technique is investigated. To verify the functionality of each CPU module, the variable-control approach which verifies the CPU modules progressively by comparing with the standard ones is explored. The experiment cases have been carried out for six years, and the course survey results showed that the new experiment design with the new implementation approaches had improved the teaching quality of the computer organization experiment significantly.