Implementation of Interleaved Dual Boost Converter Utilizing FPGA for PWM

被引：0
|
作者：
Suraj, S. [1 ]
Soman, Sarun [2 ]
Jijesh, J. J. [1 ]
机构：
[1] SVCE, E&CE, Bangalore, Karnataka, India
[2] Manipal Inst Technol, Manipal, Karnataka, India
来源：
2016 IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT) | 2016年
关键词：
Interleaved Dual Phase; Ripple Cancellation; FPGA;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Boost converter with high power has turned into the key part of the power framework that enables power to be completely used. The novel way to accomplish a decreased current ripple and voltage ripple for dc chopper is actualized. Typical boost converter is interleaved to stop high input current stress on the switches. Interleaved Dual Boost Converter has two boost converter worked in parallel and controlled utilizing interleaved strategy with same frequency and phase shift. This method permits assembling a high productive and compact converter. In this paper different parameters of the interleaved dual boost converter are contrasted with a conventional boost converter for an output of 70V, 2A. The outcomes demonstrate that this converter accomplishes a superior performance.
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页码：79 / 83
页数：5
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