3D integrated scalable focal-plane processor array

被引：0

作者：

Foeldesy, Peter ^{[1
]}

Zarandy, Akos ^{[1
]}

Rekeczky, Csaba ^{[1
]}

Roska, Tamas ^{[1
]}

机构：

[1] Hungarian Acad Sci, Comp & Automat Res Inst, Analog & Neural Comp Lab, Budapest, Hungary

来源：

2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3 | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The ASIC implementation of a 64x64 sized mixed-signal Cellular Visual Microprocessor architecture with digital processors is described. Measurement results are shown. The architecture is composed of a regular photosensor readout circuit array, prepared for 3D sensor integration, an array of identical SIMD processing elements. and central program scheduler. The processing architecture supports cluster formation of differently parameterized arrays.

引用

页码：954 / 957

页数：4

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