Efficient systolic architecture for implementation of 2-D discrete cosine transform

Recently, an efficient systolic array has been suggested by Chang and Wu[1] for the computation of discrete cosine transform (DCT), which involves only real arithmetic operations. In this paper, we have suggested another systolic array for implementing the DCT which has the same hardware requirement and yields the same throughput as that of [1]. The proposed linear array is complimentary to the existing array [1] in a sense that the output of the proposed arrays may be fed as the input for the existing arrays. This feature of the linear arrays has been utilised for designing a bilayer structure for computing the 2-D DCT. It Is Interesting to note that the proposed structure for the 2-D DCT does not require any hardware/time for the transposition of the intermediate results. The desired transposition is achieved by orthogonal alignment of the linear arrays of the upper layer with respect to those of the lower layer. The proposed structure provides high throughput of computation due to fully pipelined processing and massive parallelism employed in the bilayer architecture.