Defect Tolerance for Nanoscale Crossbar-Based Devices

被引：1
|
作者：
Tehranipoor, Mohammad [1 ]
Rad, Reza M. P. [2 ]
机构：
[1] Univ Connecticut, Storrs, CT 06269 USA
[2] Univ Maryland Baltimore Cty, Baltimore, MD 21228 USA
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2008年 / 25卷 / 06期
关键词：
Circuit faults; CMOS integrated circuits; Fault diagnosis; Logic functions; Nanoscale devices; Redundancy; Routing;
D O I：
10.1109/MDT.2008.162
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The need for defect maps and per-chip placement and routing limits the efficiency of test and defect tolerance techniques in nanoscale crossbar-based devices. The authors propose a method using two simulation programs that circumvents these difficulties to find fault-free implementations of logic functions on defective crossbars.
引用
收藏
页码：549 / 559
页数：11
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