Correlated Bayesian Model Fusion: Efficient Performance Modeling of Large-Scale Tunable Analog/RF Integrated Circuits

Tunable circuit has emerged as a promising methodology to address the grand challenge posed by process variations. Efficient high-dimensional performance modeling of tunable analog/RF circuits is an important yet challenging task. In this paper, we propose a novel performance modeling approach for tunable circuits, referred to as Correlated Bayesian Model Fusion (CBMF). The key idea is to encode the correlation information for both model template and coefficient magnitude among different knob configurations by using a unified prior distribution. The prior distribution is then combined with a few simulation samples via Bayesian inference to efficiently determine the unknown model coefficients. Two circuit examples designed in a commercial 32nm SOI CMOS process demonstrate that C-BMF achieves more than 2x cost reduction over the traditional state-of-the-art modeling technique without surrendering any accuracy.