A CMOS up-conversion mixer in 0.18 m technology for IEEE 802.11a WLAN application

This paper describes a 3.5-GHz up-conversion mixer core utilized in a two-step transmitter architecture in compliance with IEEE 802.11a WLAN application. The architecture is based on current-draining folded architecture and is implemented in 0.18-m CMOS technology, which alleviates the need of bulky resonator integration. The main advantages of the introduced mixer topology are high linearity and high isolation. The low-voltage architecture consumes 5.17 mA of current from 1.8-V supply and shows -2.09-dBm IIP 3 and -9.82-dBm IP 1dB . The proposed architecture observes an output power of -43.69 dBm at the up-converted 3.7 GHz sideband, with -30 dBm and -10 dBm of input baseband and local oscillator power, respectively.