P-n junction peripheral current analysis using gated diode measurements

The total reverse current in p-n junctions sets the leakage and power dissipation limits of integrated circuits. In modern junctions it is practically fully attributed to the peripheral component, additionally enhanced by the reduction of the junction size due to the increase of the integration scale. This peripheral generation current in modern diodes is caused by the surface generation underneath the thick field oxide surrounding the structure, which typically contains a high density of interface traps. A modified method to investigate the peripheral reverse current in a silicon p-n junction diode, is proposed and validated. Its useful advantage is related to the fact that very simple and practically a single diode measurement is needed for the peripheral current analysis, instead of the tedious measurement and extraction procedures for a set of diodes. The newly proposed method is based on the analysis of a new mode of the current-voltage characteristics of a gated diode structure, linked to the generation associated with the depletion at the Si - thick SiO2 interface. It is analysed instead of the standard gated diode measurements based on the depletion under the thin (gate) oxide, which are shown to be only weakly correlated with the p-n junction peripheral current. The new analysis method gives about forty times higher sensitivity compared to direct junction peripheral current measurements, allowing to reduce the test device perimeter and dimensions, without decrease of the measurement resolution for interface states.