A Reduced Switch Multilevel Inverter for Harmonic Reduction

被引:0
|
作者
Valsan, Nikhil K. [1 ]
Joseph, K. D. [1 ]
机构
[1] Govt RIT, Dept Elect Engn, Kottayam, Kerala, India
关键词
H-bridge inverter; multilevel inverter(MLI); power quality; Total Harmonic Distortion(THD); TOPOLOGY;
D O I
暂无
中图分类号
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号
0807 ; 0820 ;
摘要
A reduced switch topology for multilevel inverters is presented in this paper. This makes use of normal H bridge inverter with some structural modifications. Almost all the demerits of the conventional multilevel inverters is rectified by the proposed topology. Further it has inherent improved advantages too. The structure of inverter and the modulation strategies associated with the modulation scheme are also being discussed in this paper. The proposal is validated by extensive simulation studies.
引用
收藏
页数:4
相关论文
共 50 条
  • [1] A Review On Multilevel Inverter with Reduced Switch Count
    Vijayaraja, L.
    Kumar, S. Ganesh
    Rivera, M.
    [J]. 2016 IEEE INTERNATIONAL CONFERENCE ON AUTOMATICA (ICA-ACCA), 2016,
  • [2] Modified Reduced Switch Symmetrical Multilevel Inverter
    Mathew, Ronak
    Agarwal, Shobha
    [J]. PROCEEDINGS OF 2017 IEEE INTERNATIONAL CONFERENCE ON CIRCUIT ,POWER AND COMPUTING TECHNOLOGIES (ICCPCT), 2017,
  • [3] Hybrid Optimization Based Harmonic Minimization in Three Phase Multilevel Inverter With Reduced Switch Topology
    Yabalar, Mehmet Halil
    Ercelebi, Ergun
    [J]. IEEE ACCESS, 2024, 12 : 71010 - 71023
  • [4] Hybrid optimization algorithm applied for selective harmonic elimination in multilevel inverter with reduced switch topology
    Sarika D. Patil
    Sumant G. Kadwane
    [J]. Microsystem Technologies, 2018, 24 : 3409 - 3415
  • [5] Novel Reduced Switch Multilevel Inverter Suitable for Photovoltaic Application with Selective Harmonic Elimination Control
    Bana, Prabhat Ranjan
    Panda, Kaibalya Prasad
    Panda, Gayadhar
    [J]. IEEE INDICON: 15TH IEEE INDIA COUNCIL INTERNATIONAL CONFERENCE, 2018,
  • [6] Hybrid optimization algorithm applied for selective harmonic elimination in multilevel inverter with reduced switch topology
    Patil, Sarika D.
    Kadwane, Sumant G.
    [J]. MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2018, 24 (08): : 3409 - 3415
  • [7] Comparative Analysis of Harmonic Reduction in Multilevel Inverter
    Karnik, Neha
    Singla, Deepshikha
    Sharma, P. R.
    [J]. 2012 IEEE FIFTH POWER INDIA CONFERENCE, 2012,
  • [8] Analysis of Cascaded Multilevel Inverter with a Reduced Number of Switches for Reduction of Total Harmonic Distortion
    Muralikumar, Kola
    Ponnambalam, P.
    [J]. IETE JOURNAL OF RESEARCH, 2023, 69 (01) : 295 - 308
  • [9] New Reduced Switch Multilevel Inverter for PV Applications
    Abdoli, Hesamodin
    Khorsandi, Amir
    Eskandari, Bahman
    Moghani, Javad Shokrollahi
    [J]. 2020 11TH POWER ELECTRONICS, DRIVE SYSTEMS, AND TECHNOLOGIES CONFERENCE (PEDSTC), 2020,
  • [10] A comprehensive analysis of reduced switch count multilevel inverter
    Kumawat, R.K.
    Palwalia, D.K.
    [J]. Australian Journal of Electrical and Electronics Engineering, 2020, 17 (01): : 13 - 27