Exploiting vanishing polynomials for equivalence verification of fixed-size arithmetic datapaths

被引:3
|
作者
Shekhar, N [1 ]
Kalla, P [1 ]
Enescu, F [1 ]
Gopalakrishnan, S [1 ]
机构
[1] Univ Utah, Dept Elect & Comp Engn, Salt Lake City, UT 84112 USA
关键词
D O I
10.1109/ICCD.2005.52
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper addresses the problem of equivalence verification of high-level/RTL descriptions. The focus is on datapath-oriented designs that implement univariate polynomial computations over fixed-size bit-vectors. When the size (m) of the entire datapath is kept constant, fixed-size bit-vector arithmetic manifests itself as polynomial algebra over finite integer rings of residue classes Z(2m). The verification problem then reduces to that of checking equivalence of over Z(2m): in other words, to prove f(x)%2(m) equivalent to g(x)%2(m). This paper transforms the equivalence verification problem into proving (f(x)-g(x))%2(m) equivalent to 0. Exploiting the theory of vanishing polynomials overfinite integer rings, a systematic algorithmic procedure is derived to establish whether or not a given polynomial vanishes (always evaluates to 0) over Z2(m). Experiments demonstrate the effectiveness of our approach over contemporary techniques.
引用
收藏
页码:215 / 220
页数:6
相关论文
共 7 条
  • [1] Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra
    Shekhar, N
    Kalla, P
    Enescu, F
    Gopalakrishnan, S
    ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2005, : 291 - 296
  • [2] Equivalence checking method for fixed-point arithmetic datapaths
    Li, Donghai
    Ma, Guangsheng
    Hu, Jing
    Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics, 2009, 21 (01): : 27 - 32
  • [3] Equivalence verification of arithmetic datapaths with multiple word-length operands
    Shekhar, Namrata
    Kalla, Priyank
    Enescu, Florian
    2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS, 2006, : 822 - +
  • [4] Simulation bounds for equivalence verification of arithmetic datapaths with finite word-length operands
    Shekhar, Namrata
    Kalla, Priyank
    Meredith, M. Brandon
    Enescu, Florian
    PROCEEDINGS OF FORMAL METHODS IN COMPUTER AIDED DESIGN, 2006, : 179 - +
  • [5] Asymptotic equivalence of fixed-size and varying-size determinantal point processes
    Barthelme, Simon
    Amblard, Pierre-Olivier
    Tremblay, Nicolas
    BERNOULLI, 2019, 25 (4B) : 3555 - 3589
  • [6] Verification of Fixed-Point Datapaths with Comparator Units Using Constrained Arithmetic Transform (CAT)
    Sarbishei, O.
    Radecka, K.
    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 592 - 595
  • [7] Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
    Gopalakrishnan, Sivaram
    Kalla, Priyank
    Meredith, M. Brandon
    Enescu, Florian
    IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, : 143 - +