Low-Voltage MOS Current Mode Logic Multiplexer

被引：0

作者：

Gupta, Kirti ^{[1
]}

Pandey, Neeta ^{[1
]}

Gupta, Maneesha ^{[2
]}

机构：

[1] Delhi Technol Univ, Dept Elect & Commun Engn, Delhi, India

[2] Netaji Subhash Inst Technol, Dept Elect & Commun Engn, Delhi, India

来源：

RADIOENGINEERING | 2013年 / 22卷 / 01期

关键词：

MOS current mode logic; low-voltage; triple-tail cell; SOURCE-COUPLED LOGIC; DESIGN; CIRCUIT;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a new low-voltage MOS current mode logic (MCML) multiplexer based on the triple-tail cell concept is proposed. An analytical model for static parameters is formulated and is applied to develop a design approach for the proposed low-voltage MCML multiplexer. The delay of the proposed low-voltage MCML multiplexer is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML multiplexer is analyzed for the three design cases namely high-speed, power-efficient, and low-power. Finally, a comparison in performance of the proposed low-voltage MCML multiplexer with the traditional MCML multiplexer is carried out for all the cases.

引用

页码：259 / 268

页数：10

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