Side-channel Resistant Soft Core Processor for Lightweight Block Ciphers

Lightweight cryptographic algorithms which provide moderate security at low cost, especially in very-light power-, energy, and resource-constrained processors, are an important topic of research in the context of the Internet of Things (IoT). Current cryptographic contests and standardization efforts seek to evaluate side-channel resistance of lightweight ciphers on multiple platforms, including resource-constrained 8-bit microprocessors. Using a custom-designed reconfigurable soft core processor on an FPGA, we implement four ciphers, SIMON, PRESENT, LED, and TWINE, and evaluate them for vulnerability to differential power analysis (DPA) using the t-test leakage detection methodology and an open-source test bench (FOBOS). We then adapt and modify techniques used in previous cipher hardware implementations to protect the soft core processor against 1st order DPA. Improved resistance to DPA is verified using the t-test and the FOBOS test bench. No modifications to cipher source code are required for the protected soft core, meaning that software programmers are insulated from the requirement to learn side-channel resistance techniques. A single DPA-resistant soft core instance, which can load and protect all four ciphers simultaneously (where target cipher is selected by the user at run-time), uses 392 slices in the Virtex-7 FPGA - an average of 98 slices per protected cipher.