High-density low-power-operating DRAM device adopting 6F2 cell scheme with novel S-RCAT structure on 80nm feature size and beyond

被引：7

作者：

Oh, HJ ^{[1
]}

Kim, JY ^{[1
]}

Kim, JH ^{[1
]}

Park, SG ^{[1
]}

Kim, DH ^{[1
]}

Kim, SE ^{[1
]}

Woo, DS ^{[1
]}

Lee, YS ^{[1
]}

Ha, GW ^{[1
]}

Park, JM ^{[1
]}

Kang, NJ ^{[1
]}

Kim, HJ ^{[1
]}

Hwang, YS ^{[1
]}

Kim, BY ^{[1
]}

Kim, DI ^{[1
]}

Cho, YS ^{[1
]}

Choi, JK ^{[1
]}

Lee, BH ^{[1
]}

Kim, SB ^{[1
]}

Cho, MH ^{[1
]}

Kim, YI ^{[1
]}

Choi, J ^{[1
]}

Shin, DW ^{[1
]}

Shim, MS ^{[1
]}

Choi, WT ^{[1
]}

Lee, GP ^{[1
]}

Park, YJ ^{[1
]}

Lee, WS ^{[1
]}

Ryu, BI ^{[1
]}

机构：

[1] Samsung Elect Co, Semicond R&D Div, Technol Dev Team 1, Yongin 449711, Kyunggi Do, South Korea

来源：

PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2005年

关键词：

D O I：

10.1109/ESSDER.2005.1546614

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, the DRAM device composed of 6F(2) open-bit-line memory cell with 80nm feature size is developed. Adopting 6F(2) scheme instead of customary 8F(2) scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F(2) accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F(2), TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell V-th so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) is introduced. It is the improved scheme of RCAT used in 8F(2) scheme. By adopting S-RCAT, V-th can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.

引用

页码：177 / 180

页数：4

共 1 条

[1] Design and process integration for high-density, high-speed, and low-power 6F2 cross point MRAM cell
Asao, Y
Kajiyama, T
Fukuzumi, Y
Amano, M
Aikawa, H
Ueda, T
Kishi, T
Ikegawa, S
Tsuchida, K
Iwata, Y
Nitayama, A
Shimura, K
Kato, Y
Miura, S
Ishiwata, N
Hada, H
Tahara, S
Yoda, H
[J]. IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 571 - 574

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