Highly cost effective and high performance 65nm S3 (Stacked Single-crystal Si) SRAM technology with 25F2, 0.16um2 cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications

被引：0

作者：

Jung, SM ^{[1
]}

Rah, Y ^{[1
]}

Ha, T ^{[1
]}

Park, H ^{[1
]}

Chang, CL ^{[1
]}

Lee, S ^{[1
]}

Yun, JH ^{[1
]}

Cho, W ^{[1
]}

Lim, H ^{[1
]}

Park, J ^{[1
]}

Jeong, J ^{[1
]}

Son, B ^{[1
]}

Jang, J ^{[1
]}

Choi, B ^{[1
]}

Cho, H ^{[1
]}

Kim, K ^{[1
]}

机构：

[1] Samsung Elect, R&D Ctr, Yongin, South Korea

来源：

2005 Symposium on VLSI Technology, Digest of Technical Papers | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：220 / 221

页数：2

共 5 条

[1] 65nm high performance SRAM technology with 25F2, 0.16um2 S3 (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications
Lim, H
Jung, SM
Rah, Y
Ha, T
Park, H
Chang, C
Cho, W
Park, J
Son, B
Jeong, J
Cho, H
Choi, B
Kim, K
PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2005, : 549 - 552
[2] The revolutionary and truly 3-dimensional 25F2 SRAM technology with the smallest S3 (stacked single-crystal Si) cell, 0.16um2, and SSTFT (stacked single-crystal thin film transistor) for ultra high density SRAM
Jung, SM
Jang, J
Cho, W
Moon, J
Kwak, K
Choi, B
Hwang, B
Lim, H
Jeong, J
Kim, J
Kim, K
2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2004, : 228 - 229
[3] Highly area efficient and cost effective double stacked S3(stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM
Jung, SM
Lim, H
Cho, WS
Cho, HS
Yeo, CD
Kang, YH
Bae, DG
Na, J
Kwak, KH
Choi, BY
Kim, SJ
Jeong, JH
Chang, YC
Jang, JH
Kim, JH
Kim, K
Ryu, BI
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 265 - 268
[4] Novel 3-dimensional 46F2 SRAM technology with 0.294um2 S3 (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)
Jang, JH
Jung, SM
Kang, YH
Cho, WS
Moon, JH
Yeo, CD
Kwak, KH
Choi, BH
Hwang, BJ
Jung, WR
Kim, SJ
Kim, JH
Na, JH
Lim, H
Jeong, JH
Kim, K
ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2004, : 445 - 448
[5] High speed and highly cost effective 72M bit density S3SRAM technology with doubly stacked Si layers, peripheral only CoSix layers and tungsten shunt W/L scheme for standalone and embedded memory
Jung, Soon-Moon
Lim, Hoon
Yeo, Chadong
Kwak, Kunho
Son, Byoungkeun
Park, Hanbyung
Na, Jonghoon
Shim, Jae-Joo
Hong, Changmin
Kim, Kinam
2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 82 - +

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