Fault-Injection Testing: FIT-Ability, Optimal Procedure and Tool for FPGA-Based Systems SIL Certification

被引：0

作者：

Kharchenko, V. ^{[1
]}

Sklyar, V. ^{[1
]}

Odarushchenko, O.

Ivasuyk, A.

机构：

[1] Natl Aerosp Univ NE Zhukovsky KhAI, Kharkov, Ukraine

来源：

PROCEEDINGS OF IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS 2013) | 2013年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Challenges related to verification and validation (VV) of FPGA-based safety critical I&C systems (FICS) are analyzed. One of the mandatory techniques applied in process of VV and certification to requirements of IEC 61508 according with safety integrity level (SIL) is the fault insertion or injection testing (FIT). Specific features of FICS SIL-certification and FIT are described. Concept of FITability, some theoretical issues and algorithm of the optimal FIT procedure taking into account different points and means of fault injection are suggested. The developed technique and tool VTP has been applied to verify modules of FPGA-based platform RadICS during SIL-certification.

引用

页数：5

共 9 条

[1] FAULT INSERTION TESTING OF FPGA-BASED NPP I&C SYSTEMS: SIL CERTIFICATION ISSUES
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