Design of high-speed analog-to-digital interface in digital technologies

被引：0

作者：

Uyttenhove, K ^{[1
]}

Steyaert, M ^{[1
]}

机构：

[1] Katholieke Univ Leuven, ESAT, MICAS, B-3001 Heverlee, Belgium

来源：

ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS | 2001年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Analog design in deep sub-micron digital technologies is a reality now and poses severe challenges to the circuit designer. Trends in digital technologies as well as their effects on analog circuits are discussed. The typical speed-power-accuracy trade-off in analog design is revised with respect to the technological modifications. A new speed model includes slew rate behaviour together with settling behaviour. Calculations show a possible increase in power for future generations of high speed analog-to-digital converters.

引用

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页码：493 / 496

页数：4

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