Efficient Digital Predistortion Using Sparse Neural Network

被引:17
|
作者
Tanio, Masaaki [1 ]
Ishii, Naoto [2 ]
Kamiya, Norifumi [2 ]
机构
[1] NEC Corp Ltd, RF Power Amplifiers & Digital Signal Proc Tech Wi, Kawasaki, Kanagawa 2118666, Japan
[2] NEC Corp Ltd, Syst Platform Res Labs, Kawasaki, Kanagawa 2118666, Japan
来源
IEEE ACCESS | 2020年 / 8卷 / 08期
关键词
Digital predistortion; generalized memory polynomial; memory polynomial; neural network; pruning technique; MODEL; VOLTERRA;
D O I
10.1109/ACCESS.2020.3005146
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper proposes an efficient neural-network-based digital predistortion (DPD), named as envelope time-delay neural network (ETDNN) DPD. The method complies with the physical characteristics of radio-frequency (RF) power amplifiers (PAs) and uses a more compact DPD model than the conventional neural-network-based DPD. Additionally, a structured pruning technique is presented and used to reduce the computational complexity. It is shown that the resulting ETDNN obtained after applying pruning becomes so sparse that its complexity is comparable to that of conventional DPDs such as memory polynomial(MP) and generalized memory polynomial (GMP), while the degradation in performance due to the pruning is negligible. In an experiment on a 3.5-GHz GaN Doherty power amplifier (PA), our method with the proposed pruning had only one-thirtieth the computational complexity of the conventional neural-network-based DPD for the same adjacent channel leakage ratio (ACLR). Moreover, compared with memory-polynomial-based digital predistortion, our method with the proposed pruning achieved a 7-dB improvement in ACLR, despite it having lower computational complexity.
引用
收藏
页码:117841 / 117852
页数:12
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