Generic techniques and CAD tools for automated generation of FPGA layout

This paper presents an automated method of generating an FPGA layout. The main purpose of developing a generator is to reduce the overall FPGA design time with limited area penalty. This generator works in two phases. In the first phase, it generates a partial layout using generic parameterized algorithms. The partial layout is generated to obtain a fast bitstrearn configuration mechanism, an efficient power routing and a balanced clock distribution network. In the second phase, the generator completes the remaining layout using automatic placer and router. This two-phase technique allows better maneuvering of the layout according to initial constraints. The proposed method is validated by generating the layout of an island-style FPGA which includes hardware support for the mitigation of Single Event Upsets (SEU). The FPGA layout is generated using a symbolic standard cell library which allows easy migration to any layout technology. This layout is successfully migrated to 130nm technology.