Symbol-rate timing error detectors for DSL transceivers

Symbol-rate timing error detectors are derived which allow to optimize the synchronization of single carrier DSL transceivers. The synchronizer input signal in DSL receivers does not have the ideal characteristics which are assumed by many synchronizer algorithms in the literature. Impairments and distortion of the DSL channel require a decision feedback equalizer in the receiver. A timing error detector in the control loop has optimal performance, if the jitter is minimal. Therefore timing jitter due to additive noise and due to synchronizer self-noise is generally described and analyzed as a function of the synchronizer implementation, channel characteristics and noise scenario. New timing error detector implementations are systematically derived which have better synchronizer performance than timing error detectors known from the literature.