Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K-Best Detector for Large-Scale MIMO Systems

被引:28
|
作者
Peng, Guiqiang [1 ]
Liu, Leibo [1 ]
Zhou, Sheng [2 ]
Xue, Yang [1 ]
Yin, Shouyi [1 ]
Wei, Shaojun [1 ]
机构
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
[2] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China
关键词
Large-scale MIMO; K-best; sorted QR decomposition; lattice reduction; Cholesky decomposition; VLSI; LATTICE-REDUCTION; IMPLEMENTATION; DESIGN; FRAMEWORK; UPLINK; ZF;
D O I
10.1109/TSP.2018.2799191
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
As a branch of sphere decoding, the K-best method has played an important role in detection in large-scale multiple-input-multiple-output (MIMO) systems. However, as the numbers of users and antennas grow, the preprocessing complexity increases significantly, which is one of the major issues with the K-best method. To address this problem, this paper proposes a preprocessing algorithm combining Cholesky sorted QR decomposition and partial iterative lattice reduction (CHOSLAR) for K-best detection in a 64-quadrature amplitude modulation (QAM) 16 x 16 MIMO system. First, Cholesky decomposition is conducted to perform sorted QR decomposition. Compared with conventional sorted QR decomposition, this method reduces the number of multiplications by 25.1% and increases parallelism. Then, a constant-throughput partial iterative lattice reduction method is adopted to achieve near-optimal detection accuracy. This method further increases parallelism, reduces the number of matrix swaps by 45.5%, and reduces the number of multiplications by 67.3%. Finally, a sorting-reduced K-best strategy is used for vector estimation, thereby, reducing the number of comparators by 84.7%. This method suffers an accuracy loss of only approximately 1.44 dB compared with maximum likelihood detection. Based on CHOSLAR, this paper proposes a fully pipelined very-large-scale-integration architecture. A series of different systolic arrays and parallel processing units achieves an optimal tradeoff among throughput, area consumption, and power consumption. This architectural layout is obtained via TSMC 65-nm 1P9M CMOS technology, and throughput metrics of 1.40 Gbps/W (throughput/power) and 0.62 Mbps/kG (throughput/area) are achieved, demonstrating that the proposed system is much more efficient than state-of-the-art designs.
引用
收藏
页码:1860 / 1875
页数:16
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