SPEEDUP-AWARE HISTORY-BASED TILING ALGORITHM FOR THE HEVC STANDARD

被引：0

作者：

Storch, Iago ^{[1
]}

Palomino, Daniel ^{[1
]}

Zatt, Bruno ^{[1
]}

Agostini, Luciano ^{[1
]}

机构：

[1] Fed Univ Pelotas UFPel, PPGC, Ctr Engn, Grp Architecture & Integrated Circuits GACI, Pelotas, RS, Brazil

来源：

2016 IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING (ICIP) | 2016年

关键词：

Parallel Video Coding; Workload Balance; Speedup; Tiles;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a history based tiling algorithm aiming at the increase of speedup when using Tiles. The algorithm is composed of two independent steps that use workload history information to define the vertical and horizontal boundaries of the Tiles. The workload distribution of previous frames are used as reference to perform the tiling of the current frame exploiting the temporal similarity between neighboring frames. Experimental results show that the proposed algorithm outperforms the speedup when compared to uniform tiling by 6.85% on average for tested sequences, besides, there is no significant complexity increase and similar coding efficiency results. When compared to related works the proposed solution also presents better speedup results.

引用

页码：824 / 828

页数：5

共 27 条

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