On the nature and inadequacies of transport timing delay constructs in VHDL descriptions

The design of VHDL transport delay uses an implicit assumption that bus with multiple taps, only one tap is a driver and the signal reaches tile other taps delayed only by the time necessary for the electro-magnetic propagation. Perturbation due to reflection at the intermediate taps, is ignored and this results in incorrect timing behavior. This paper proposes extensions to VHDL grammar and defines new semantics in the language to accurately capture and model tile transport timing behavior of buses with multiple, distinct taps.