FPGA Implementation of Polar Format Algorithm for Airborne Spotlight SAR Processing

To satisfy the demand of real-time processing of airborne synthetic aperture radar (SAR), the polar format algorithm (PFA) is designed and implemented based on FPGA. In this design, the complicated two-dimensional interpolation of the canonic PFA is implemented using the principle of chirp-scaling (PCS) to improve the efficiency, the Floating-Point IP core and pipeline structure is applied to the realize high-speed floating-point-number computation, and an efficient scheme employed to control the read and write mode of DDR3 SDRAM is brought up to realize the transposition of matrix data demanded by the algorithm. The system is built on the KC705 evaluation board, and in a test with real SAR data, it takes approximately 1s to process 4096*4096 single-precision floating-point pixels with reasonable imaging result, when the system works at 200MHz.