A Survey on Cache Tuning from a Power/Energy Perspective

被引:34
|
作者
Zang, Wei [1 ]
Gordon-Ross, Ann [1 ]
机构
[1] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
基金
美国国家科学基金会;
关键词
Design; Algorithms; Performance; Cache tuning; cache partitioning; cache configuration; power saving; energy saving; HIGH-PERFORMANCE; REDUCTION TECHNIQUES; INSTRUCTION CACHE; REDUCING LEAKAGE; PAGE PLACEMENT; EARLY-STAGE; SIMULATION; ENERGY; POWER; SYSTEM;
D O I
10.1145/2480741.2480749
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Low power and/or energy consumption is a requirement not only in embedded systems that run on batteries or have limited cooling capabilities, but also in desktop and mainframes where chips require costly cooling techniques. Since the cache subsystem is typically the most power/energy-consuming subsystem, caches are good candidates for power/energy optimizations, and therefore, cache tuning techniques are widely researched. This survey focuses on state-of-the-art offline static and online dynamic cache tuning techniques and summarizes the techniques' attributes, major challenges, and potential research trends to inspire novel ideas and future research avenues.
引用
收藏
页数:49
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