Polyhedral Parallel Code Generation for CUDA

被引:124
|
作者
Verdoolaege, Sven [1 ,2 ]
Carlos Juega, Juan [3 ]
Cohen, Albert [1 ,2 ]
Ignacio Gomez, Jose [3 ]
Tenllado, Christian [3 ]
Catthoor, Francky
机构
[1] INRIA, Paris, France
[2] Ecole Normale Super, Paris, France
[3] Univ Complutense Madrid, E-28040 Madrid, Spain
关键词
Algorithms; Performance; Polyhedral model; GPU; CUDA; code generation; compilers; loop transformations; C-to-CUDA; Par4All; PPCG; AFFINE SCHEDULING PROBLEM; EFFICIENT SOLUTIONS;
D O I
10.1145/2400682.2400713
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This article addresses the compilation of a sequential program for parallel execution on a modern GPU. To this end, we present a novel source-to-source compiler called PPCG. PPCG singles out for its ability to accelerate computations from any static control loop nest, generating multiple CUDA kernels when necessary. We introduce a multilevel tiling strategy and a code generation scheme for the parallelization and locality optimization of imperfectly nested loops, managing memory and exposing concurrency according to the constraints of modern GPUs. We evaluate our algorithms and tool on the entire PolyBench suite.
引用
收藏
页数:23
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