Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code

被引:7
|
作者
Zacharopoulos, Georgios [1 ]
Ferretti, Lorenzo [1 ]
Ansaloni, Giovanni [1 ]
Di Guglielmo, Giuseppe [2 ]
Carloni, Luca [2 ]
Pozzi, Laura [1 ]
机构
[1] Univ Svizzera Italiana, Lugano, Switzerland
[2] Columbia Univ, New York, NY USA
基金
瑞士国家科学基金会;
关键词
Hardware/Software Co-Design; Application Specific Processors; Accelerators Identification; Software Analysis;
D O I
10.1109/ICCD46524.2019.00024
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Hardware design is a difficult task. Beside ensuring functional correctness of an implementation, hardware developers are confronted with multiple and often conflicting constraints, such as performance and area cost targets, that require lengthy explorations. This issue is compounded when considering the acceleration of complex applications, of which some parts are implemented in software, and others are accelerated in hardware. Hardware/Software partitioning must be settled early in the development cycle, and is far from trivial, since at this stage detailed performance measurements are not available, while wrong choices can lead to vastly sub-optimal solutions or to wasted implementation efforts. To address this challenge, we present a framework to automatically identify, from un-modified software code, software segments that are promising candidates for hardware acceleration, to evaluate their potential speedup and resource requirements, and to select a subset of them under resource constraint. Our strategy is based on Intermediate Representation (IR) analysis passes, which we embed in the LLVM compiler toolchain, and does not require any time-consuming synthesis. We explore its effectiveness on the reference software implementation of a complex application, the H.264 Decoder from University of Illinois, and demonstrate that our methodology selects higher-performance sets of accelerators, when compared to strategies only based on profiling information.
引用
收藏
页码:129 / 137
页数:9
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