Improvement of die shift by solder self-alignment for fan-out package process applications

Fan-out wafer level package (FO-WLP) technology has emerged and been applied in a range of 3D package platforms, such as mobile application processors (APs), as well as wearable and automotive devices. Die shift is one of the largest processing issues in fan-out package technologies. To solve the die shift issue, a new process utilizing molten solder in flip-chip technology for FO-WLP process applications was proposed. In this study, the die shift value was investigated in reduced solder volume conditions by changing the printed solder quantity on the substrate and under bump metallurgy (UBM) pad, and by changing the locations of the UBM pads. Sn-3.0Ag-0.5Cu (SAC305) and Sn-3.5Ag solder pastes were printed on the Cu-organic solderability preservation (Cu-OSP) or electroless nickel electroless palladium immersion gold (ENEPIG) pads using the stencil printing method. When the solder volume is reduced, the maximum value of the die shift was greater than 1 mu m, however after applying the SAC305 solder and ENEPIG pads, the die shift value was less than 0.5 mu m. These results can improve the die shift value in cases of reduced solder volume conditions that require a narrower solder joint gap height between the chip and substrate, as well as limited UBM pads locations for chip design in FO-WLP process applications.