Delay and Power Optimized Adaptive Filter using Distributed Arithmetic

Adaptive filters are the core functional block in the digital signal processing. Adaptive FIR filter with Block LMS algorithm is basically used to reduce the power consumption. In this paper a distributed arithmetic (DA) is used for implementation of BLMS algorithm. It is used to calculate the inner product by shifting and accumulating of partial products. These are stored in look up table (LUT). DA based BLMS algorithm is used to reduce the area. The area is reduced as both convolution operation and correlation operation is performed by using the same LUT. The distributed arithmetic based design uses a look up table sharing for computation of the weight increment terms and filter outputs of BLMS algorithm. This results in less use of adders which is a major component of DA based structures. The LUT based weight updating for BLMS algorithm is suggested in the paper. For the implementation of BLMS adaptive digital filter, we have developed a parallel architecture. Parallel processing is used to increase the speed. Parallel processing results in high throughput. It requires less number of LUT access for every output than the existing structure, for higher block size. In the design, number of adders does not increase with filter order. The number of flip flops also does not dependent on block size. The advantage of the structure is reduction in its delay and area delay product (ADP). The adaptive filter will be multiplierless, which reduces the complexity of the circuit. We have also observed increase in its PSNR. Thus a DA based implementation of adaptive FIR filter using BLMS algorithm is area efficient and highly computational.