Speeding Up in Distributed SystemC Simulations

SystemC is becoming a popular framework for System on Chip (SoC) design and verification. Innovation in SoC design does not come easily. Smaller features, faster speeds, and intricate digital logic require more simulation resources. SystemC is designed to run the entire simulation solely on one processor. Though designers can model concurrent threads, those threads are executed sequentially as one process. In this paper, we analyze the efficiency of the main approaches to distribute the simulation of SystemC models and we present our own approach which is based on the analyzed ones. We compare the effectiveness of our approach with previous ones using a model with n RISC processors and a single n-port RAM.