Multiple Fault Diagnosis and Test Power Reduction Using Genetic Algorithms

In this paper, a novel method for multiple fault diagnosis is proposed using Genetic Algorithms. Fault diagnosis plays a major role in VLSI Design and Testing. The input test vectors required for testing should be compact and optimized. Genetic Algorithm is a search technique to find approximate solutions to optimization and search problems. The proposed technique uses binary strings as a substitute for chromosomes. The chromosomes (test vectors) are initialized randomly and their fitness value is evaluated. Genetic operations selection, crossover and mutation are performed on this initialized set (initial population) to reproduce better test vectors. The test vectors thus generated are reordered by using a reordering algorithm. The total switching activity among the reordered test vectors is thus optimized and hence the reduction of test power.