Geometric-mean based current-mode CMOS multiplier/divider

被引：0
|
作者：
López-Martín, AJ [1 ]
Carlosena, A [1 ]
机构：
[1] Univ Publ Navarra, Dept Ingn Elect & Elect, Arrosadia S-n, Pamplona 31006, Spain
来源：
ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI | 1999年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A novel current-mode analog multiplier/divider based on a voltage-translinear implementation of a geometric-mean circuit is presented, featuring favorable precision and wide dynamic range. It is suitable for standard CMOS fabrication and can be successfully applied in a wide range of analog systems. Two versions, based on stacked and up-down voltage-translinear loops, respectively, are described and verified by simulation.
引用
收藏
页码：342 / +
页数：2
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