Hardware design and implementation of packet fair queuing algorithms for the quality of service support in the high-speed internet

The increasing amount of real-time traffic carried over the Internet requires end-to-end quality of service (QoS) support. To this end, the QoS Schedulers, that are implemented in routers, assign the available bandwidth resources to packet flows according to their respective allocated rates. Packet Fair Queuing (PFQ) schedulers can provide fair service and low end-to-end delay bound to the traffic flows. However, they have higher implementation complexity compared to other algorithms, because of the requirements of tracking the system state, and searching for the packet to get service among all flows, that are queued at the outgoing interface. QoS scheduling is a data plane functionality, which requires hardware implementation for high speed router interfaces. The previous works on hardware implementation of PFQ schedulers are specific to certain algorithms, and they do not provide any results on real hardware platforms. In this paper, we present a general hardware design framework for PFQ schedulers, and apply this framework to the WF(2)Q+ PFQ algorithm to demonstrate its properties. We carry out the entire implementation of the WF(2)Q+ algorithm on an FPGA, and evaluate its performance with real traffic flows. In addition, we implement WFQ as a second PFQ algorithm to demonstrate the generality of the framework. (C) 2012 Elsevier B.V. All rights reserved.