Design and Realization of Real-Time Spectrum Analysis System Based on DSP Builder

被引:2
|
作者
Meng Zengchui [1 ]
Wan Xin [1 ]
机构
[1] Tianjin Polytech Univ, Tianjin, Peoples R China
关键词
FPGA; FFT_IP core; DSP Builder; Verilog HDL;
D O I
10.1109/IMCCC.2012.254
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
A method of designing real-time spectrum analysis based on FPGA is put forward in this article and the characteristic of the FFT_IP core is described in detail. This system uses the Altera DSP Builder tool converting the built algorithm model into the hardware description language of FPGA directly. It ensures that FFT algorithm model based on FPGA reduce the difficulty of development and design, and it is easy to modify and test. Verilog hardware description language is used to realize the sampling control, loading data and VGA display driver. Finally, the program is simulated in Quartus II software tools, and realized on FPGA. The practice shows that the spectrum analysis system is applied to the system on the real-time requirements strictly.
引用
收藏
页码:1077 / 1080
页数:4
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